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PS12 Quad Power Sequencing Controller
Features
Power supply sequencer with four outputs Power-up and power-down sequencing Six programmable delays Maximum 90V supply voltage Input voltage window comparator Low power supply current (500A typical) 16-Lead SOIC Package
General Description
Many systems require that their power supplies are enabled and disabled sequentially in order to reduce transient current demand on the power bus, or to avoid damage to components having multiple supply voltages such as microprocessors, ASICs, MEMS drivers, etc. The PS12 incorporates a power-up delay timer, a window voltage comparator, 4 open drain enable outputs, and 6 enable delay timers. The enable delays are individually programmable for both the power-up (ABCD) and the powerdown (DCBA) sequence. Power-up and power-down are controlled by a window comparator formed by the ON and OV voltage comparators. VIN voltage within the window initiates power-up; VIN voltage outside of the window maintains or initiates power-down. The power-up sequence may be interrupted while in progress. The power-down sequence, once initiated, cannot be interrupted until it is brought to completion.
Applications
Reduction of transient current demand and protection of sensitive loads Telecom and networking systems High voltage MEMS and display driver supplies
Typical Application Circuit
+12V
15 R1 3 VIN ON
1 VEE PSA 11 ENA +12V CONVERTER OUT
R2
4
OV
PSB
12
ENA
R3
+5V CONVERTER
OUT
PS12NG
PSC 2 PUD PSD TAB 5 RAB TBC 6 RBC TCD 7 RCD TDC 8 RDC TCB 9 RCB TBA 10 RBA 14 ENA +1.8V CONVERTER OUT 13 ENA +3.3V CONVERTER OUT
CPUD
PS12
Ordering Information
Device PS12
-G indicates package is RoHS compliant (`Green')
Pin Configuration
Package Option 16-Lead SOIC PS12NG-G
VEE 1 PUD 2 ON 3 OV 4 16 NC 15 VIN 14 PSD 13 PSC 12 PSB 11 PSA 10 TBA 9 TCB
TAB 5
Absolute Maximum Ratings
Parameter VIN1 PSA...PSD ON, OV
1 2 1
TBC 6
Value -0.3V...+100V -0.3V...+100V -0.3V...+8V 2kV -40OC...+85OC -40OC...+125OC -65OC...+150OC
TCD 7 TDC 8
16-Lead SOIC
(top view)
ESD (all pins except VIN, PSA...PSD) Operating ambient temperature Operating junction temperature Storage temperature
Pin Configuration
Top Marking
PS12NG
YWW LLLLLLLL
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Notes: 1. Referenced to VEE 2. HBM, 1.5k, 100pF
Bottom Marking
CCCCCCCCC AAA
Thermal Resistance
Package 16-Lead SOIC
(PCB Layout dependent)
Y = Last Digit of Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin A = Assembler ID* = "Green" Packaging
*May be part of top marking
ja 65K/W to 120K/W
Block Diagram
PS12
ON PU 1.20V PD 1.00V OV
VIN
INTERNAL VOLTAGE REGULATOR
PSA
PSB
PD 1.20V PU 1.00V
CONTROL LOGIC
PSC
PSD
12 A VEE 1.20 V
PUD
TAB R AB
TBC R BC
TCD R CD
TDC R DC
TCB R CB
TBA R BA
C PUD
2
PS12
Electrical Characteristics
(TJ = 25C unless otherwise specified. Voltages referenced to VEE, VVIN = +4.5V...+90V. Values marked with * apply over the full temperature range.)
Symbol Supply (VIN) VVIN IVIN
Parameter
Min
Typ
Max
Units
Conditions
Supply voltage Supply current
4.5 -
500 400
90 625 -
V A
* -
--VIN = 36V, RT = 2M VIN = 12V, RT = 2M
Input Voltage Monitor (ON) VONPU VONPD VHY ION Power-up threshold Power-down threshold Power-up/Power-down hysteresis Input Current 1.16 1.06 1.22 1.12 100 1 1.28 1.18 V V mV nA * * VON Rising VON Falling -----
Input Voltage Monitor (OV) VOVPD VOVPU VHY IOV Power-down threshold Power-up threshold Power-up/power-down hysteresis Input current 1.16 1.06 1.22 1.12 100 1 1.28 1.18 V V mV nA * * VOV Rising VOV Falling -----
Power Supply Enable Outputs (PSA, PSB, PSC, PSD) ILKG VSAT High state leakage current Low state output voltage 10 100 A mV * VPS = 90V PS = HiZ IPS = 1mA PS = Low
Power-up Delay (PUD) IPUD VPUD RDISCH Output current Threshold voltage Discharge FET ON resistance -8.4 1.15 -12 1.20 500 -16 1.25 A V ----IDISCH = 1mA
Power Supply Enable Timing (TAB, TBC, TCD, TDC, TCB, TBA) RT TPSPS(MAX) TPSPS(MIN) Timing resistance range Maximum PS-to-PS delay Minimum PS-to-PS delay 50 160 4.0 200 5.0 2000 240 6.0 k ms ms --RT = 2M RT = 50k
3
PS12
Pin Description
Pin # 15 1 Function VIN VEE Description Power supply pins. VIN positive with respect to VEE. The outputs PSA thru PSD are pulled to a logic low state upon application of power. Hookup pin for the power-up-delay (PUD) timing capacitor. 2 3 4 5 6 7 8 9 10 11 PUD Pin pulls capacitor to ground upon application of power. (See timing diagram) ON OV TAB TBC TCD TDC TCB TBA PSA Power supply enable output pins. These four pins control loads, such as DC/DC converter modules, load switches, ICs, etc. Configured with open drain output stages. On power-up, right after expiration of the PUD delay, the sequencer asserts PSA, and subsequently asserts PSB, PSC and PSD observing the delays, programmed by the (TAB, TBC, and TCD) pins. On power-down, the sequencer deasserts PSD, and subsequently deasserts PSC, PSB, and PSA observing the delays, programmed by the (TAB, TBC, and TCD) pins. No connect On power-down, the resistor at TDC determines the delay between the falling transitions of PSD and PSC; similarly, TCB relates to ( PSC / PSB ), and TBA to ( PSB / PSA ). Hookup pins for timing resistors. On power-up, the resistor at TAB determines the delay between the rising transitions of PSA and PSB; similarly, TBC relates to ( PSB / PSC ), and TCD to ( PSC / PSD ). Input pin of the ON comparator. Rising transition initiates power-up sequence. Input pin of the OV comparator. Rising transition initiates the power-down sequence.
12
PSB
13
PSC
14 16
PSD NC
4
PS12
Oscillograms
The figures of typical waveforms are organized in the following way: Figure 1, 2, 3, 4 5, 6 7, 8 9 10 Function PS (A, B, C, D) ON, PUD, PS (A, B, D) PUD, PS (A, B) OV, PUD, PS (A, B) ON, PS (A, B, C) Description Power-up and power-down delays. Delay times around 5ms and 200ms. ON pin detail. Fig.6. shows a power-down / power-up sequence. PUD pin detail; PSA is asserted when voltage at PUD pin about 1.2V. PUD pin resets when PSB is deasserted. OV pin detail. Overvoltage returns to voltage window. Partial power-up sequence. Power-down triggered by loss of valid ON.
Fig.1
Fig.2
Fig.3
Fig.4
5
PS12
Fig.5 Fig.6
Fig.7
Fig.8
Fig.9
Fig.10
6
PS12
Functional Description
The PS12 provides power-up and power-down sequencing for devices such as power supply modules, load switches, ICs, etc. The four outputs PSA thru PSD are configured with open drain drivers, which are typically used to power supply modules. Some systems may require level-shifting or isolating drivers. Upon application of power, the power-up delay timer is reset and the enable outputs PSA thru PSD are de-asserted.
Enable Outputs at Low VIN
The internal circuits of the PS12 can be expected to provide well-defined outputs at a power supply voltage of about 3.3V and above. At lower power supply voltages, the existence of poorly defined output levels should typically not be an issue if the PS12 and the controlled loads share the same supply, since the loads may not be adequately biased as well. Some caution is warranted when the controlled loads are independently powered and the power supply voltage to the PS12 is inadequate or ill-defined.
Window Comparator
The state of the four PS outputs and the associated powerup and power-down sequencing is controlled by a window comparator formed by the ON and OV voltage comparators. These comparators define a voltage window having thresholds programmed by an external resistive divider. The ON comparator defines the lower threshold of the window, while the OV comparator defines the upper threshold of the window. Both comparator thresholds feature 200mV hysteresis.
Delay Time Considerations
The PS12 is characterized for enable to enable delay times between 5ms and 200ms, which should cover most applications. Initial characterization of this device shows excellent linearity between delay time and programming resistance for a delay time in the range of 2.5ms to 5 seconds. Shorting of a programming pin is not advised, and may reduce long term reliability, as internal circuits are not dimensioned for sourcing the resultant pin current.
Power-up and Power-down Sequence
Power supply voltage moving into the window causes the start of a power-up sequence. The sequence consists of the power-up delay, programmed by CPUD, and the subsequent assertion of the PS outputs in the sequence ABCD using the enable to enable delays (TAB, TBC, TCD), as programmed by the resistors (RAB, RBC, RCD). Power supply voltage moving outside the window causes the start of a power-down sequence. The sequence consists of the de-assertion of the most recently asserted PS output, typically PSD, and subsequent de-assertion of other asserted PS outputs in the sequence DCBA using the enable delays (TDC, TCB, TBA), as programmed by the resistors (RDC, RCB, RBA). The power-up sequence may be terminated prematurely by a power-down sequence. On the other hand, the power-down sequence is latching in nature; once power-down is initiated, the sequence is brought to completion regardless of changes in the state of the window comparator. After the power-down sequence is completed, a new power-up sequence may start, depending on the state of the window comparator at that time.
Power-up Delay (PUD)
The power-up delay is set by the time required to charge the CPUD capacitor to 1.2V. The PUD pin sources a current of 12A, resulting in a delay time of 100ms per F. Charging continues past the power-up delay until a voltage of about 4V is reached. An internal voltage comparator at the PUD pin inhibits the power-up sequence, should the CPUD capacitor not be discharged before initiating the power-up delay. Discharge of the CPUD capacitor occurs during the powerdown sequence. The discharge transistor is turned on at the end of the sequence when PSA is the last remaining asserted output.
7
PS12
Programming ON and UV
V IN
Start the design by programming the power-up voltage. The power-down voltage VINONPD is fixed at 83.3% of the powerup voltage. Next, program the overvoltage power down voltage VOVPD by selecting the multiplying factor R2 / R3, knowing VINONPU. A numerical example: VIN = 12V and [R1, R2, R3] = [107k, 4.99k, 9.09k], results in the following:
ON
R1
R2
ONPU 1.20V ONPD 1.10V
(1) RDIV = 121.1k, (2) IDIV = 99.1A, (3) [VINONPU, VINONPD, VINOVPD, VINOVPU] = [10.32V, 8.60V, 15.98V, 13.32V]. Note the following:
OV
VINOVPD VINONPU
R3
VOVPD R3 R 1.20 R2 + R3 = 1+ 2 = = VONPU 1.20 R3 R3 R 2 + R3
OVPD 1.20V OVPU 1.10V
Programming the Power-up Delay
The ON and OV inputs draw negligible current, allowing the use of a high impedance divider. A divider current between 10A and 100A is more than adequate. RDIV = R1 + R2 + R3 IDIV V = IN RDIV The power-up delay (TPUD) is set by the time required to charge the CPUD capacitor to the threshold voltage VPUD: VPUD = 1.20V IPUD = 12A TPUD = CPUD * VPUD IPUD
VIN thresholds can be determined from the following: ON Power-up: ON Power-down: OV Power-down: OV Power-up: VONPU = 1.20V VINONPU VONPU = R2 + R3 RDIV VINONPD V = ONPD R2 + R3 RDIV VINOVPD VOVPD = RDIV R3 VINOVPU VOVPU = RDIV R3
A numerical example: A 100nF capacitor results in a TPUD of 12ms.
Programming the PS to PS Delay
The PS to PS delays are set by the six timing resistors. Delay time and resistance are related as follows: TPSPS = KT * RT KT = 100 ns
VONPD = 1.00V
VOVPD = 1.20V
A numerical example: A resistance of 100k results in a delay time of 10ms.
VOVPU = 1.00V
8
PS12
Timing Diagram
VIN OVPD VIN OVPU VIN ONPU VIN ONPD VIN ONPD VIN VIN OVPD VIN OVPU
TPUD
PUD
PSA TAB TAB
PSB TBC TBC
PSC TCD TDC
PSD
9
PS12
16-Lead SOIC (Narrow Body) Package Outline (NG)
9.90x3.90mm body, 1.75mm height (max), 1.27mm pitch
16
D
1
Note 1 (Index Area D/2 x E1/2)
E1
E
L2 Gauge Plane
1 L1
L
Seating Plane
Top View
A
View B
View B
h A A2 e
Seating Plane
h
Note 1
A1
b A
Side View
View A-A
Note 1: This chamfer feature is optional. If it is not present, then a Pin 1 identifier must be located in the index area indicated.The Pin 1 identifier may be either a mold, or an embedded metal or marked feature.
Symbol MIN Dimension (mm) NOM MAX
A 1.35 1.75
A1 0.10 0.25
A2 1.25 1.65
b 0.31 0.51
D 9.80 9.90 10.00
E 5.80 6.00 6.20
E1 3.80 3.90 4.00
e 1.27 BSC
h 0.25 0.50
L 0.40 1.27
L1 1.04 REF
L2 0.25 BSC
0
O
1 5O 15O
8O
JEDEC Registration MS-012, Variation AC, Issue E, Sept. 2005. Drawings not to scale.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.)
Doc.#DSFP-PS12 NR042707
10

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